1/4 rev. a structure silicon monolithic integrated circuit product clock generator with built-in vcxo type BU3058FV feature to generate clocks for the digital-tv. clock signals are generated by connecting crystal oscillator. built-in vcxo has the va riable width of typ105ppm. absolute maximum ratings (ta=25 ) parameter symbol ratings unit supply voltage vdd -0.3 4.0 v input voltage vin -0.3 vdd+0.3 v storage temperature range ts t g -55 125 power dissipation pd 450 1 mw 1 a measure value at mounting on 70x 70x1.6mm glass epoxy substrate. in the case of exceeding ta=25c, 4.5mw should be reduced per 1c. the radiation-resistance design is not carried out. operation is not guaranteed. operating conditions parameter symbol ratings unit supply voltage vdd 3.135 3.465 v input ?h? voltage vih 0.8vdd vdd v input ?l? voltage vil 0.0 0.2vdd v operating temperature topr -10 75 frequency control voltage vc 0.0 vdd v
2/4 rev. a electrical characteristics vdd=3.3v, ta=25c, crystal frequency=27.0000 00mhz, at no load, unless otherwise specified parameter symbol limit unit conditions min. typ. max. output h voltage voh vdd-0.4 v ioh=4.0ma output l voltage vol 0.4 v iol=4.0ma operating circuit current idd 40.0 52.0 ma output no load input h current 1 iuph -1.5 1.5 a pdb terminal,vih=vdd input h current 2 idnh 19.0 69.0 136.5 a test terminal,vih=vdd input h current 3 idirh -1.5 1.5 a vctrl, sel1, sel2 terminal,vih=vdd input l current 1 iupl -126.0 -53.0 -17.0 a pdb terminal,vil=0.0v input l current 2 idnl -1.5 1.5 a test terminal,vil=0.0v input l current 3 idirl -1.5 1.5 a vctrl, sel1, sel2 terminal,vil=0.0v crystal pullability fp 80 105 130 ppm 0Q vctrl Q vdd this is a guarantee with only ic. the arrangement with a crystal maker is required separately about crystal variation. block diagram 7:sel1 8:sel2 10:test test terminal,with pull-down 4:vctrl 1:xin 16:xout 11:clk54m 14:clkout pll1 pll2 9:clk27m v cxo output select control 15:pdb power-down control terminal with pull-up table of output frequency crystal frequency=27.000000mhz mode no. sel1 sel2 14pin 11pin 9pin clkout clk54m clk27m l l 66.000000mhz 54.00 0000mhz 27.000000mhz l h 74.250000mhz 54.00 0000mhz 27.000000mhz h l 77.000000mhz 54.00 0000mhz 27.000000mhz h h 82.000000mhz 54.000000mhz 27.000000mhz
3/4 rev. a package outline, appearance of marker pin function pin no. pin name function 1 xin crystal input terminal 2 avdd1 power supply for vcxo 3 avss1 gnd for vcxo 4 vctrl vcxo control input terminal 5 avdd2 power supply for pll-analog 6 avss2 gnd for pll-analog 7 sel1 clkout output control terminal1 8 sel2 clkout output control terminal2 9 clk27m 27.000000mhz output 10 test test terminal with pull-down 11 clk54m 54.000000mhz output 12 vss gnd for pll-digital 13 vdd power supply for pll-digital 14 clkout 66.000000mhz / 74.250000mhz / 77.000000mhz / 82.000000mhz output 15 pdb power-down control terminal,with pull-up 16 xout crystal output terminal cautions on use BU3058FV basically, mount ics to the printed circuit board for use. (if the ics are not mounted to the printed circuit board, the characteristics of ics may not be fully demonstrated.) mount 0.1f capacitors in the vicinity of the ic pins between 2pin (avdd1), 3pin (avss1), and 5pin(avdd2), 6pin(avss2), and 12pin (vss), 13pin (vdd) respectively. to obtain accurate frequency, capacitance (pf) need to be placed between 3pin (avss1) and 1pin (xin), 3pin (avss1) and 16pin(xout). depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the power supply and gnd terminal. for emi protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU3058FV from the printed circuit board or to insert a capacitor (of 1 ? or less), which bypasses hi gh frequency desired, between the power supply and the gnd terminal. for ics with more than one power supply, it is possible that rush current may flow instantaneously due to the internal powering sequence and delays. therefore, give s pecial consideration to power coupling capacitance, power wiring, width of gnd wiring, and routing of wiring. 3058f lot no. ssop-b16
4/4 rev. a cautions on use common absolute maximum ratings an excess in the absolute maximum ratings, such as supply vo ltage, temperature range of operat ing conditions, etc., can break d own devices, thus making imposs ible to identify breaking mode such as a short circuit or an open circuit. if any special mode excee ding the absolute maximum ratings is assumed, consideration should be given to take physical safety measur es including the use of fuses, etc. operating conditions these conditions represent a range within which characteristics can be provided approximately as expected. the electrical chara cteristics are guaranteed under the conditions of each parameter. reverse connection of power supply connector the reverse connection of power supply connector can break down ics. take protective measures against the breakdown due to the reverse connection, such as mounting an external diode between the power supply and the ic?s power supply terminal. power supply line design pcb pattern to provide low impedance for the wiring between the power supply and the gnd lines.in this regard, for the d igital block power supply and the analog block power supply, even though these power supplies has the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. for the gnd line, give considerat ion to design the patterns in a similar manner. furthermore, for all power supply terminals to ics, mount a capacitor between the power supply and the gnd terminal. at the sam e time, in order to use an electrolytic capacitor, t horoughly check to be sure the characteristics of the capacitor to be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant. gnd voltage make setting of the potential of the gnd terminal so that it will be maintained at the minimum in any operating state. furtherm ore, check to be sure no terminals are at a potential lower than the gnd voltage including an actual electric transient. short circuit between terminals and erroneous mounting in order to mount ics on a set pcb, pay thorough attention to the direction and offset of the ics. erroneous mounting can break down the ics. furthermore, if a short circuit occurs due to foreign matters entering between te rminals or between the terminal and the p ower supply or the gnd terminal, the ics can break down. operation in strong electromagnetic field be noted that using ics in the strong electromagnetic field can malfunction them. inspection with set pcb on the inspection with the set pcb, if a capacitor is connected to a low-impedance ic terminal, the ic can suffer stress. there fore, be sure to discharge from the set pcb by each process. furthermore, in order to mount or dismount the set pcb to/from the jig for the i nspection process, be sure to turn off the power supply and then mount the set pcb to the jig. after the completion of the inspection, be sure to turn off the power supply and then dismount it from the jig. in additi on, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set pcb. input terminals in terms of the construction of ic, parasitic elements are inevitably formed in relation to potential. the operation of the par asitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a voltage lower than the gnd respectively, so that any parasitic element will operate. furthermore, do not apply a voltage to the input terminals when no power supply voltage is appl ied to the ic. in addition, even if the power supply volt age is applied, apply to the input terminals a voltage lower than the power supply vo ltage or within the gu aranteed value of electrical characteristics. ground wiring pattern if small-signal gnd and large-current gnd are provided, it will be recommended to separate the large-current gnd pattern from t he small-signal gnd pattern and establish a single ground at the refere nce point of the set pcb so that resistance to the wiring p attern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal gnd. pay attention not t o cause fluctuations in the gnd wiring pattern of external parts as well. external capacitor in order to use a ceramic capacitor as the external capacitor, determine the constant with c onsideration given to a degradation in the nominal capacitance due to dc bias and cha nges in the capacitance due to temperature, etc.
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